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LogicSim is an affordable and user-friendly Verilog simulator for Asic and FPGA design verification. It offers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog...
License:Shareware | Price: $99.00 | Size: 9.4 MB | Downloads (34 )
PLD2 is a language allowing the programmer new control of run- and compile-time. The underlying instruction set and output file format are not wired in to the compiler. PLD2 comes with x86 and Windows EXE...
License:Shareware | Price: $49.95 | Size: 281 KB | Downloads (61 )
| Files 1-2 of 2 |